Lehrveranstaltung: Hardware Verification and Quality Assessment (6607-511)

Personen:

• Prof. Dr. rer. nat. habil. Hans-Joachim Wunderlich (verantwortlich)

Lehrform:

Vorlesung mit Übung

SWS:

4

Inhalt:

Complex integrated circuits and systems are hardly designed fault free at first go. Also during production defects and an imperfect yield have to be expected. The course deals with the basic techniques to find and locate faults and defects in the design and in the manufactured, integrated system. The discussed methods are applied with the help of commercial and academic tools in exercises and labs.,The course comprises:-Validation: Simulation and emulation in different design levels.-Formal verification: Equivalence checking and model checking.-Test: Fault simulation and test generation.-Debug and diagnosis.

Literatur:

-G. D. Hachtel, F. Somenzi: Logic Synthesis and Verification Algorithms, 2006
-K. L. McMillan: Symbolic Model Checking, 1993
-L.-T. Wang, C.-W. Wu, X. Wen: VLSI Test Principles and Architectures - Design for Testability, 2006
-M. L. Bushnell, V. D. Agrawal: Essentials of Electronic Testing, 2005
-R. Drechsler, B. Becker: Graphenbasierte Funktionsdarstellung, 2000
-S. Hassoun, T. Sasao: Logic Synthesis and Verification, 2002
-S. Minato: Binary Decision Diagrams and Applications for VLSI CAD, 1996
-T. Kropf: Introduction to Formal Hardware Verification, 1999

Veranstaltungsort:

Stuttgart-Stadt

Modul:

• 6607-510 Hardware Verification and Quality Assessment (Pflicht)