Course: Hardware Verification and Quality Assessment (6607-511)

Persons:

• Prof. Dr. rer. nat. habil. Hans-Joachim Wunderlich (verantwortlich)

Type of Course:

lecture with exercise

In-Class Hours Per Week:

4

Contents:

*

Literature:

-G. D. Hachtel, F. Somenzi: Logic Synthesis and Verification Algorithms, 2006
-K. L. McMillan: Symbolic Model Checking, 1993
-L.-T. Wang, C.-W. Wu, X. Wen: VLSI Test Principles and Architectures - Design for Testability, 2006
-M. L. Bushnell, V. D. Agrawal: Essentials of Electronic Testing, 2005
-R. Drechsler, B. Becker: Graphenbasierte Funktionsdarstellung, 2000
-S. Hassoun, T. Sasao: Logic Synthesis and Verification, 2002
-S. Minato: Binary Decision Diagrams and Applications for VLSI CAD, 1996
-T. Kropf: Introduction to Formal Hardware Verification, 1999

Location:

Stuttgart-Stadt

Module:

• 6607-510 Hardware Verification and Quality Assessment (compulsory)